1. Field of the Invention
The present invention relates to a digital-control-type phase-composing circuit system in which two clock signals having a phase difference therebetween are weighted through a control signal to compose an output clock signal having a phase between those of the two clock signals. More particularly, the present invention relates to a digital-control-type phase-composing circuit system capable of improving jitter resistance and expanding the lock range.
2. Background Art
In a delay locked loop (DLL) circuit, a digital-control-type phase-composing circuit system which combines two clock signals having a phase difference therebetween by weighting the signals is used (see, for example, Japanese Patent Laid-Open No. 2001-217682 and U.S. Pat. No. 5,485,490).
FIG. 4 is a block diagram showing a conventional digital-control-type phase-composing circuit system. A phase-composing circuit 11 composes an output clock signal having a phase between the phases of two clock signals i-CLK and q-CLK different from each other by weighting these clock signals through a control signal, as shown in FIG. 5. This output clock signal and a reference clock signal (or input data) are input to a flip-flop circuit 12.
A binary phase comparison circuit 13 compares the phase of the output clock signal and the phase of the reference clock signal. An up/down counter 14 increments or decrements the count value on the basis of the result of comparison and outputs the count value as a control signal to the phase-composing circuit 11. Thus, feedback to the control signal is provided such that the phase of the output clock signal is equalized to the phase of the reference clock signal, thereby locking the output clock signal to the reference clock signal.
However, if the operating frequency of the counter is reduced to improve the jitter resistance of the phase-composing circuit, the lock range is reduced. Conversely, if the operating frequency of the counter is increased to expand the lock range, the phase-composing circuit is easily affected by high-frequency jitter when the reference clock signal and the output clock signal become in phase with each other.
Also, in a situation where the reference clock signal and the output clock signal are in a positional relationship shown in FIG. 6, the phase comparison circuit may output low level (L) when it should output high level (H), if the edge of the reference clock signal fluctuates due to jitter. If the reference clock signal has such jitter, the output clock signal from the phase comparison circuit is fluctuated by the jitter so that the value of the up/down counter in the following stage is changed unnecessarily frequently, thus causing jitter in the output clock signal. For this reason, it is difficult to apply the conventional digital-control-type phase-composing circuit system particularly to a clock and data recovery (CDR) circuit which processes data containing a large amount of jitter.